The circuit below describes a 4-to-1 multiplexer with data inputs 13, 12, 1 and lo and selects S1 and So. Draw the multiplexer circuit described by the VHDL below.
O InOSel <= NOT S1 AND NOT SO AND 10
O In1Sel <= NOT S1 AND SO AND 11;
O in2Sel S1 AND NOT S0 AND 12;
O In3Sel <= S1 AND SO AND 13;