Answer: (i). C of P1 = 3.2 ˣ 10⁻⁸ nF and
C of P2 = 2.90 ˣ 10⁻⁸ nF
(ii). Vdd of P1 = 0.9V
Vdd of P2 = 0.9V
Explanation:
To begin solving this problem, we would define the parameters given;
we have that the capacitance load (CL) = Dynamic Power / (0.5 × V² × Clock rate)
The average capacitance load ;
For C of P1 processor,
P1 is given thus;
CL = 90 / (0.5 × 1.25² × 3.6 × 10⁹) = 3.2 ˣ 10⁻⁸ nF
For C of P1 processor,
Average capacitive loads
P2:
CL = 40 / (0.5 ˣ 0.9² ˣ 3.4 ˣ 10⁹) = 2.90 ˣ 10⁻⁸ nF
(ii). given that the voltage is reduced by 10% for P1 and P2 processor
For Vdd of P1:
Therefore the total power dissipated power = Voltage ˣ Leakage current
∴ the total dissipated power = 10 + 90 = 100W
Recalling we have;
P = V × I
100 = 1.25 × I
leakage current (I) = 80 A
so total dissipated power × 0.9 = 90W
90 = 1.25α × 80
α = 0.9V
For Vdd of P2:
total dissipated power = 30 + 40 = 70W
so inputting power
70 = 0.9 × I
I = 78, where I is the leakage current
∴ total dissipated power × 0.9 = 63W
solving this gives
63 = 0.9α × 78
where α = 0.9V
cheers i hope this helps